As is well known in this specific technical field, there exists a growing demand from the market, and especially from the smart card market, for integration in a single semiconductor electronic device of both ROM (Read Only Memory) circuits and non-volatile, but electrically erasable, memories such as EEPROMs and/or Flash EEPROMS. Filling this demand calls for a significantly more complicated manufacturing process than a process used to create only a single one of these memories, as the technologies involved in providing either circuit types are not fully compatible. Accordingly, production costs become higher, and achieving high yield rates is made more difficult. In addition, continuing advances in cryptographic techniques require the use of codes of increasing size, in terms of number of bits, which are not easily decrypted by reverse engineering methods.
It is also recognized that an array of ROM cells is essentially an array of MOS transistors having conventional source, drain, and gate terminals, and threshold voltages which are set during their fabrication process. The threshold is also differentiated such that, for any given bias of the transistor gate terminal, it becomes possible to determine which cells are in the `on` (logic 1) state and which are instead in the `off` (logic 0) state by means of a suitable sensing circuit. Telling which cells are in the logic 1 state and which are in the logic 0 state is usually achieved by implanting or not implanting the source and drain junctions during the step of implanting these transistor regions.
This prior approach provides cells with a logic value of 1 and/or 0, without a preliminary optical analysis enabling them to be discerned. Other approaches allow the logic value of 1 or 0 to be determined based on the presence or absence of a transistor.
There is no current technology available which can provide a multi-level ROM structure, that is, a structure which can store several logic values in each memory cell.